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Communication Buses: I2C vs SPI vs UART

The protocol comparison every embedded interview starts with — wiring, speed, arbitration and failure modes.

BoschQualcommContinentalTexas Instruments

Key formulas

bit time = 1 / baud; e.g. 9600 baud → 104 µs/bit
UART baud rate: Oversampling receivers sample at 16× the baud to centre the sample point.
throughput ≈ bits_per_transfer × f_SCL efficiency (incl. ACK, addressing)
I2C throughput: Effective data rate is well below f_SCL because of address + ACK overhead per byte.

▸UART: asynchronous, 2 wires (TX/RX), point-to-point, both sides must agree on baud rate; frame = start + data + optional parity + stop.
▸I2C: synchronous, 2 wires (SDA/SCL) with pull-ups, multi-device via 7-bit addresses, multi-master with clock synchronization and arbitration.
▸SPI: synchronous, 4 wires (MOSI/MISO/SCK/CS), full-duplex, fastest of the three, one CS line per slave (or daisy-chained).
▸I2C speeds: 100 kHz standard, 400 kHz fast, 3.4 MHz high-speed. SPI commonly 10–50+ MHz.
▸I2C open-drain logic needs external pull-up resistors (typ. 2.2–10 kΩ); a stuck-low bus means a hung slave.
▸Choose UART for debug consoles, I2C for low-pin-count sensors, SPI for high-throughput flash/displays/ADCs.

Aspect	UART	I2C	SPI
Wires	2 (TX, RX)	2 (SDA, SCL)	4 (MOSI, MISO, SCK, CS)
Clock	None (async)	Shared (SCL)	Shared (SCK)
Devices	Strictly 1-to-1	Multi-drop, addressed	Multi-drop via chip selects
Duplex	Full (separate lines)	Half-duplex	Full-duplex
Speed	Up to ~1–5 Mbaud	100k–3.4 MHz	Tens of MHz+
Master/slave	Peers	Multi-master capable	Single master typical

I2C byte transfer:
  START → [ADDR7 + R/W] → ACK → [DATA8] → ACK → … → STOP
  SDA changes only while SCL is LOW (change on HIGH = START/STOP)

1. Which protocol is asynchronous?

2. I2C data line (SDA) may only change when SCL is…

3. In SPI, the clock polarity/phase settings are called…

4. Which bus needs a separate chip-select line per slave (in the basic form)?