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8051/ARM Architecture & Interrupts

Register sets, memory maps, interrupt latency and prioritisation — the groundwork of every embedded systems round.

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Key formulas

  • 1 machine cycle = 12 clock periods (classic 8051)

    8051 machine cycle: At 12 MHz crystal, one machine cycle = 1 µs — used for timing calculations in interviews.

  • t_overflow = (2^n − count) × T_machine

    Timer overflow period: For Timer0 mode-1 (16-bit) loading TH0/TL0 with 65536−N gives an interrupt every N cycles.

Cheat sheet

  • ▸8051 basics: 8-bit CPU, 128B internal RAM, 4 register banks (R0–R7), 4KB on-chip ROM (classic), two 16-bit timers, 5 interrupt sources.
  • ▸ARM is a load-store RISC: arithmetic operates on registers only; memory access via LDR/STR instructions.
  • ▸Interrupt latency = time from interrupt assertion to first instruction of the ISR; reduced by short critical sections and nesting.
  • ▸Interrupt priority: fixed priority (8051 default) vs programmable (8051 IP register); ARM uses NVIC with programmable priorities and nesting.
  • ▸ISR etiquette: save context, keep it short, clear the interrupt flag, restore context — never busy-wait inside an ISR.
  • ▸Vector table: fixed addresses (8051: 0003H, 000BH…) vs ARM Cortex-M vector table of handler addresses at 0x00000000.

8051 vs ARM Cortex-M at a glance

Aspect8051 (classic)ARM Cortex-M
Architecture8-bit CISC-ish accumulator machine32-bit RISC load-store
Interrupts5 sources, 2-level priority, fixed vectorsNVIC: up to 240, programmable priorities, auto-stacking
MemoryHarvard (separate code/data)Modified Harvard with buses
Power featuresIdle / power-down modesMultiple sleep modes, WFI/WFE, tick-less idle

Visual

Interrupt flow (Cortex-M):
 IRQ asserted → NVIC prioritises → CPU stacks R0-R3,R12,LR,PC,xPSR
 → jumps to ISR (vector table) → ISR runs → exception return (unstack, resume)

Top 4 campus interview questions

MCQ mastery quiz

1. In the classic 8051, one machine cycle equals…

2. ARM Cortex-M interrupt priorities follow the convention…

3. Which registers does Cortex-M automatically stack on interrupt entry?

4. The 8051 PSW's RS1/RS0 bits control…