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Sequential Circuits & FSM (Moore vs Mealy)

Flip-flops, counters and finite state machines — the classic 'design a 1011 sequence detector' whiteboard question.

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Key formulas

Q(n+1) = D
Characteristic equation D-FF: D flip-flop transparently stores next-state value at the clock edge — the workhorse of FSM synthesis.
Q(n+1) = J·Q' + K'·Q
Characteristic equation JK-FF: J=K=1 toggles, J=K=0 holds — JK is the 'universal' flip-flop used to derive T and D behaviour.

▸Latches are level-triggered; flip-flops are edge-triggered — the clock edge freezes the input window.
▸Moore output depends only on state (glitch-free, +1 clock latency); Mealy output depends on state + input (fewer states, faster).
▸Every FSM needs: state register, next-state logic (combinational), output logic, and a defined reset state.
▸Sequence detector design flow: draw the state diagram → encode states (binary/one-hot/Gray) → derive next-state equations → verify with a timing trace.
▸Counters: a mod-N counter has ⌈log₂N⌉ flip-flops and unused states — design them to safely return to the count sequence.
▸One-hot encoding uses one FF per state: simple decode logic, great for FPGAs; binary encoding minimises flip-flops.

Aspect	Moore	Mealy
Output depends on	State only	State + current input
States needed	Usually more	Usually fewer
Output timing	Changes on clock edge (registered)	Can change with input (combinational)
Glitch risk	Low	Higher — outputs can ripple with inputs
Sequence-detector latency	Detects one cycle later	Detects in the same cycle

Mealy 1011 detector (partial):
  S0 --1/0--> S1 --0/0--> S2 --1/0--> S3 --1/1--> S1
  output z = 1 when input x=1 while in S3 (Mealy: same edge)

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